# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=gfx908 -verify-machineinstrs -run-pass si-fold-operands %s -o - | FileCheck %s --check-prefixes=GFX908
# RUN: llc -march=amdgcn -mcpu=gfx90a -verify-machineinstrs -run-pass si-fold-operands %s -o - | FileCheck %s --check-prefixes=GFX90A
# RUN: llc -march=amdgcn -mcpu=gfx940 -verify-machineinstrs -run-pass si-fold-operands %s -o - | FileCheck %s --check-prefixes=GFX90A

---
name: test_sgpr_init_multiuse
tracksRegLiveness: true

body: |
  ; GFX908-LABEL: name: test_sgpr_init_multiuse
  ; GFX908: bb.0:
  ; GFX908-NEXT:   successors: %bb.1(0x80000000)
  ; GFX908-NEXT:   liveins: $sgpr0, $scc
  ; GFX908-NEXT: {{  $}}
  ; GFX908-NEXT:   [[COPY:%[0-9]+]]:sgpr_32 = COPY $sgpr0
  ; GFX908-NEXT:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
  ; GFX908-NEXT:   [[V_ACCVGPR_WRITE_B32_e64_:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 [[COPY1]], implicit $exec
  ; GFX908-NEXT:   [[V_ACCVGPR_WRITE_B32_e64_1:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 [[COPY1]], implicit $exec
  ; GFX908-NEXT:   [[V_ACCVGPR_WRITE_B32_e64_2:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 [[COPY1]], implicit $exec
  ; GFX908-NEXT:   [[V_ACCVGPR_WRITE_B32_e64_3:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 [[COPY1]], implicit $exec
  ; GFX908-NEXT: {{  $}}
  ; GFX908-NEXT: bb.1:
  ; GFX908-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
  ; GFX908-NEXT:   liveins: $scc
  ; GFX908-NEXT: {{  $}}
  ; GFX908-NEXT:   [[PHI:%[0-9]+]]:agpr_32 = PHI [[V_ACCVGPR_WRITE_B32_e64_3]], %bb.0, %13.sub0, %bb.1
  ; GFX908-NEXT:   [[PHI1:%[0-9]+]]:agpr_32 = PHI [[V_ACCVGPR_WRITE_B32_e64_2]], %bb.0, %13.sub1, %bb.1
  ; GFX908-NEXT:   [[PHI2:%[0-9]+]]:agpr_32 = PHI [[V_ACCVGPR_WRITE_B32_e64_1]], %bb.0, %13.sub2, %bb.1
  ; GFX908-NEXT:   [[PHI3:%[0-9]+]]:agpr_32 = PHI [[V_ACCVGPR_WRITE_B32_e64_]], %bb.0, %13.sub3, %bb.1
  ; GFX908-NEXT:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[PHI3]]
  ; GFX908-NEXT:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[PHI2]]
  ; GFX908-NEXT:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[PHI1]]
  ; GFX908-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[PHI]]
  ; GFX908-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:areg_128_align2 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY4]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY2]], %subreg.sub3
  ; GFX908-NEXT:   [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1073741824, implicit $exec
  ; GFX908-NEXT:   [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
  ; GFX908-NEXT:   [[V_MFMA_F32_4X4X1F32_e64_:%[0-9]+]]:areg_128_align2 = V_MFMA_F32_4X4X1F32_e64 [[V_MOV_B32_e32_1]], [[V_MOV_B32_e32_]], [[REG_SEQUENCE]], 0, 0, 0, implicit $mode, implicit $exec
  ; GFX908-NEXT:   S_CBRANCH_SCC1 %bb.1, implicit $scc
  ; GFX908-NEXT: {{  $}}
  ; GFX908-NEXT: bb.2:
  ; GFX908-NEXT:   S_ENDPGM 0
  ; GFX90A-LABEL: name: test_sgpr_init_multiuse
  ; GFX90A: bb.0:
  ; GFX90A-NEXT:   successors: %bb.1(0x80000000)
  ; GFX90A-NEXT:   liveins: $sgpr0, $scc
  ; GFX90A-NEXT: {{  $}}
  ; GFX90A-NEXT:   [[COPY:%[0-9]+]]:sgpr_32 = COPY $sgpr0
  ; GFX90A-NEXT:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
  ; GFX90A-NEXT:   [[COPY2:%[0-9]+]]:agpr_32 = COPY [[COPY1]]
  ; GFX90A-NEXT:   [[COPY3:%[0-9]+]]:agpr_32 = COPY [[COPY1]]
  ; GFX90A-NEXT:   [[COPY4:%[0-9]+]]:agpr_32 = COPY [[COPY1]]
  ; GFX90A-NEXT:   [[COPY5:%[0-9]+]]:agpr_32 = COPY [[COPY1]]
  ; GFX90A-NEXT: {{  $}}
  ; GFX90A-NEXT: bb.1:
  ; GFX90A-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
  ; GFX90A-NEXT:   liveins: $scc
  ; GFX90A-NEXT: {{  $}}
  ; GFX90A-NEXT:   [[PHI:%[0-9]+]]:agpr_32 = PHI [[COPY5]], %bb.0, %13.sub0, %bb.1
  ; GFX90A-NEXT:   [[PHI1:%[0-9]+]]:agpr_32 = PHI [[COPY4]], %bb.0, %13.sub1, %bb.1
  ; GFX90A-NEXT:   [[PHI2:%[0-9]+]]:agpr_32 = PHI [[COPY3]], %bb.0, %13.sub2, %bb.1
  ; GFX90A-NEXT:   [[PHI3:%[0-9]+]]:agpr_32 = PHI [[COPY2]], %bb.0, %13.sub3, %bb.1
  ; GFX90A-NEXT:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[PHI3]]
  ; GFX90A-NEXT:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[PHI2]]
  ; GFX90A-NEXT:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[PHI1]]
  ; GFX90A-NEXT:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[PHI]]
  ; GFX90A-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:areg_128_align2 = REG_SEQUENCE [[COPY9]], %subreg.sub0, [[COPY8]], %subreg.sub1, [[COPY7]], %subreg.sub2, [[COPY6]], %subreg.sub3
  ; GFX90A-NEXT:   [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1073741824, implicit $exec
  ; GFX90A-NEXT:   [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
  ; GFX90A-NEXT:   [[V_MFMA_F32_4X4X1F32_e64_:%[0-9]+]]:areg_128_align2 = V_MFMA_F32_4X4X1F32_e64 [[V_MOV_B32_e32_1]], [[V_MOV_B32_e32_]], [[REG_SEQUENCE]], 0, 0, 0, implicit $mode, implicit $exec
  ; GFX90A-NEXT:   S_CBRANCH_SCC1 %bb.1, implicit $scc
  ; GFX90A-NEXT: {{  $}}
  ; GFX90A-NEXT: bb.2:
  ; GFX90A-NEXT:   S_ENDPGM 0
  bb.0:
    liveins: $sgpr0, $scc
    successors: %bb.1

    %0:sgpr_32 = COPY $sgpr0
    %1:vgpr_32 = COPY %0

  bb.1:
    liveins: $scc
    successors: %bb.1, %bb.2

    %8:vgpr_32 = PHI %1, %bb.0, %16, %bb.1
    %9:vgpr_32 = PHI %1, %bb.0, %17, %bb.1
    %10:vgpr_32 = PHI %1, %bb.0, %18, %bb.1
    %11:vgpr_32 = PHI %1, %bb.0, %19, %bb.1
    %12:areg_128_align2 = REG_SEQUENCE %8, %subreg.sub0, %9, %subreg.sub1, %10, %subreg.sub2, %11, %subreg.sub3
    %13:vgpr_32 = V_MOV_B32_e32 1073741824, implicit $exec
    %14:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
    %15:areg_128_align2 = V_MFMA_F32_4X4X1F32_e64 %14:vgpr_32, %13:vgpr_32, %12:areg_128_align2, 0, 0, 0, implicit $mode, implicit $exec
    %16:vgpr_32 = COPY %15.sub0
    %17:vgpr_32 = COPY %15.sub1
    %18:vgpr_32 = COPY %15.sub2
    %19:vgpr_32 = COPY %15.sub3
    S_CBRANCH_SCC1 %bb.1, implicit $scc

  bb.2:
    S_ENDPGM 0
...

---
name: test_sgpr_init_singleuse
tracksRegLiveness: true

body: |
  ; GFX908-LABEL: name: test_sgpr_init_singleuse
  ; GFX908: bb.0:
  ; GFX908-NEXT:   successors: %bb.1(0x80000000)
  ; GFX908-NEXT:   liveins: $sgpr0, $scc
  ; GFX908-NEXT: {{  $}}
  ; GFX908-NEXT:   [[COPY:%[0-9]+]]:sgpr_32 = COPY $sgpr0
  ; GFX908-NEXT:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
  ; GFX908-NEXT:   [[COPY2:%[0-9]+]]:agpr_32 = COPY [[COPY1]]
  ; GFX908-NEXT:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
  ; GFX908-NEXT:   [[COPY4:%[0-9]+]]:agpr_32 = COPY [[COPY3]]
  ; GFX908-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
  ; GFX908-NEXT:   [[COPY6:%[0-9]+]]:agpr_32 = COPY [[COPY5]]
  ; GFX908-NEXT:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
  ; GFX908-NEXT:   [[COPY8:%[0-9]+]]:agpr_32 = COPY [[COPY7]]
  ; GFX908-NEXT: {{  $}}
  ; GFX908-NEXT: bb.1:
  ; GFX908-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
  ; GFX908-NEXT:   liveins: $scc
  ; GFX908-NEXT: {{  $}}
  ; GFX908-NEXT:   [[PHI:%[0-9]+]]:agpr_32 = PHI [[COPY2]], %bb.0, %16.sub0, %bb.1
  ; GFX908-NEXT:   [[PHI1:%[0-9]+]]:agpr_32 = PHI [[COPY4]], %bb.0, %16.sub1, %bb.1
  ; GFX908-NEXT:   [[PHI2:%[0-9]+]]:agpr_32 = PHI [[COPY6]], %bb.0, %16.sub2, %bb.1
  ; GFX908-NEXT:   [[PHI3:%[0-9]+]]:agpr_32 = PHI [[COPY8]], %bb.0, %16.sub3, %bb.1
  ; GFX908-NEXT:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[PHI3]]
  ; GFX908-NEXT:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[PHI2]]
  ; GFX908-NEXT:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[PHI1]]
  ; GFX908-NEXT:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[PHI]]
  ; GFX908-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:areg_128_align2 = REG_SEQUENCE [[COPY12]], %subreg.sub0, [[COPY11]], %subreg.sub1, [[COPY10]], %subreg.sub2, [[COPY9]], %subreg.sub3
  ; GFX908-NEXT:   [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1073741824, implicit $exec
  ; GFX908-NEXT:   [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
  ; GFX908-NEXT:   [[V_MFMA_F32_4X4X1F32_e64_:%[0-9]+]]:areg_128_align2 = V_MFMA_F32_4X4X1F32_e64 [[V_MOV_B32_e32_1]], [[V_MOV_B32_e32_]], [[REG_SEQUENCE]], 0, 0, 0, implicit $mode, implicit $exec
  ; GFX908-NEXT:   S_CBRANCH_SCC1 %bb.1, implicit $scc
  ; GFX908-NEXT: {{  $}}
  ; GFX908-NEXT: bb.2:
  ; GFX908-NEXT:   S_ENDPGM 0
  ; GFX90A-LABEL: name: test_sgpr_init_singleuse
  ; GFX90A: bb.0:
  ; GFX90A-NEXT:   successors: %bb.1(0x80000000)
  ; GFX90A-NEXT:   liveins: $sgpr0, $scc
  ; GFX90A-NEXT: {{  $}}
  ; GFX90A-NEXT:   [[COPY:%[0-9]+]]:sgpr_32 = COPY $sgpr0
  ; GFX90A-NEXT:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
  ; GFX90A-NEXT:   [[COPY2:%[0-9]+]]:agpr_32 = COPY [[COPY1]]
  ; GFX90A-NEXT:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
  ; GFX90A-NEXT:   [[COPY4:%[0-9]+]]:agpr_32 = COPY [[COPY3]]
  ; GFX90A-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
  ; GFX90A-NEXT:   [[COPY6:%[0-9]+]]:agpr_32 = COPY [[COPY5]]
  ; GFX90A-NEXT:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
  ; GFX90A-NEXT:   [[COPY8:%[0-9]+]]:agpr_32 = COPY [[COPY7]]
  ; GFX90A-NEXT: {{  $}}
  ; GFX90A-NEXT: bb.1:
  ; GFX90A-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
  ; GFX90A-NEXT:   liveins: $scc
  ; GFX90A-NEXT: {{  $}}
  ; GFX90A-NEXT:   [[PHI:%[0-9]+]]:agpr_32 = PHI [[COPY2]], %bb.0, %16.sub0, %bb.1
  ; GFX90A-NEXT:   [[PHI1:%[0-9]+]]:agpr_32 = PHI [[COPY4]], %bb.0, %16.sub1, %bb.1
  ; GFX90A-NEXT:   [[PHI2:%[0-9]+]]:agpr_32 = PHI [[COPY6]], %bb.0, %16.sub2, %bb.1
  ; GFX90A-NEXT:   [[PHI3:%[0-9]+]]:agpr_32 = PHI [[COPY8]], %bb.0, %16.sub3, %bb.1
  ; GFX90A-NEXT:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[PHI3]]
  ; GFX90A-NEXT:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[PHI2]]
  ; GFX90A-NEXT:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[PHI1]]
  ; GFX90A-NEXT:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[PHI]]
  ; GFX90A-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:areg_128_align2 = REG_SEQUENCE [[COPY12]], %subreg.sub0, [[COPY11]], %subreg.sub1, [[COPY10]], %subreg.sub2, [[COPY9]], %subreg.sub3
  ; GFX90A-NEXT:   [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1073741824, implicit $exec
  ; GFX90A-NEXT:   [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
  ; GFX90A-NEXT:   [[V_MFMA_F32_4X4X1F32_e64_:%[0-9]+]]:areg_128_align2 = V_MFMA_F32_4X4X1F32_e64 [[V_MOV_B32_e32_1]], [[V_MOV_B32_e32_]], [[REG_SEQUENCE]], 0, 0, 0, implicit $mode, implicit $exec
  ; GFX90A-NEXT:   S_CBRANCH_SCC1 %bb.1, implicit $scc
  ; GFX90A-NEXT: {{  $}}
  ; GFX90A-NEXT: bb.2:
  ; GFX90A-NEXT:   S_ENDPGM 0
  bb.0:
    liveins: $sgpr0, $scc
    successors: %bb.1

    %0:sgpr_32 = COPY $sgpr0
    %1:vgpr_32 = COPY %0
    %2:vgpr_32 = COPY %0
    %3:vgpr_32 = COPY %0
    %4:vgpr_32 = COPY %0

  bb.1:
    liveins: $scc
    successors: %bb.1, %bb.2

    %8:vgpr_32 = PHI %1, %bb.0, %16, %bb.1
    %9:vgpr_32 = PHI %2, %bb.0, %17, %bb.1
    %10:vgpr_32 = PHI %3, %bb.0, %18, %bb.1
    %11:vgpr_32 = PHI %4, %bb.0, %19, %bb.1
    %12:areg_128_align2 = REG_SEQUENCE %8, %subreg.sub0, %9, %subreg.sub1, %10, %subreg.sub2, %11, %subreg.sub3
    %13:vgpr_32 = V_MOV_B32_e32 1073741824, implicit $exec
    %14:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
    %15:areg_128_align2 = V_MFMA_F32_4X4X1F32_e64 %14:vgpr_32, %13:vgpr_32, %12:areg_128_align2, 0, 0, 0, implicit $mode, implicit $exec
    %16:vgpr_32 = COPY %15.sub0
    %17:vgpr_32 = COPY %15.sub1
    %18:vgpr_32 = COPY %15.sub2
    %19:vgpr_32 = COPY %15.sub3
    S_CBRANCH_SCC1 %bb.1, implicit $scc

  bb.2:
    S_ENDPGM 0
...

---
name: test_vgpr_init
tracksRegLiveness: true

body: |
  ; GFX908-LABEL: name: test_vgpr_init
  ; GFX908: bb.0:
  ; GFX908-NEXT:   successors: %bb.1(0x80000000)
  ; GFX908-NEXT:   liveins: $vgpr0, $scc
  ; GFX908-NEXT: {{  $}}
  ; GFX908-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX908-NEXT:   [[COPY1:%[0-9]+]]:agpr_32 = COPY [[COPY]]
  ; GFX908-NEXT:   [[COPY2:%[0-9]+]]:agpr_32 = COPY [[COPY]]
  ; GFX908-NEXT:   [[COPY3:%[0-9]+]]:agpr_32 = COPY [[COPY]]
  ; GFX908-NEXT:   [[COPY4:%[0-9]+]]:agpr_32 = COPY [[COPY]]
  ; GFX908-NEXT: {{  $}}
  ; GFX908-NEXT: bb.1:
  ; GFX908-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
  ; GFX908-NEXT:   liveins: $scc
  ; GFX908-NEXT: {{  $}}
  ; GFX908-NEXT:   [[PHI:%[0-9]+]]:agpr_32 = PHI [[COPY4]], %bb.0, %12.sub0, %bb.1
  ; GFX908-NEXT:   [[PHI1:%[0-9]+]]:agpr_32 = PHI [[COPY3]], %bb.0, %12.sub1, %bb.1
  ; GFX908-NEXT:   [[PHI2:%[0-9]+]]:agpr_32 = PHI [[COPY2]], %bb.0, %12.sub2, %bb.1
  ; GFX908-NEXT:   [[PHI3:%[0-9]+]]:agpr_32 = PHI [[COPY1]], %bb.0, %12.sub3, %bb.1
  ; GFX908-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[PHI3]]
  ; GFX908-NEXT:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[PHI2]]
  ; GFX908-NEXT:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[PHI1]]
  ; GFX908-NEXT:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[PHI]]
  ; GFX908-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:areg_128_align2 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY7]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY5]], %subreg.sub3
  ; GFX908-NEXT:   [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1073741824, implicit $exec
  ; GFX908-NEXT:   [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
  ; GFX908-NEXT:   [[V_MFMA_F32_4X4X1F32_e64_:%[0-9]+]]:areg_128_align2 = V_MFMA_F32_4X4X1F32_e64 [[V_MOV_B32_e32_1]], [[V_MOV_B32_e32_]], [[REG_SEQUENCE]], 0, 0, 0, implicit $mode, implicit $exec
  ; GFX908-NEXT:   S_CBRANCH_SCC1 %bb.1, implicit $scc
  ; GFX908-NEXT: {{  $}}
  ; GFX908-NEXT: bb.2:
  ; GFX908-NEXT:   S_ENDPGM 0
  ; GFX90A-LABEL: name: test_vgpr_init
  ; GFX90A: bb.0:
  ; GFX90A-NEXT:   successors: %bb.1(0x80000000)
  ; GFX90A-NEXT:   liveins: $vgpr0, $scc
  ; GFX90A-NEXT: {{  $}}
  ; GFX90A-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX90A-NEXT:   [[COPY1:%[0-9]+]]:agpr_32 = COPY [[COPY]]
  ; GFX90A-NEXT:   [[COPY2:%[0-9]+]]:agpr_32 = COPY [[COPY]]
  ; GFX90A-NEXT:   [[COPY3:%[0-9]+]]:agpr_32 = COPY [[COPY]]
  ; GFX90A-NEXT:   [[COPY4:%[0-9]+]]:agpr_32 = COPY [[COPY]]
  ; GFX90A-NEXT: {{  $}}
  ; GFX90A-NEXT: bb.1:
  ; GFX90A-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
  ; GFX90A-NEXT:   liveins: $scc
  ; GFX90A-NEXT: {{  $}}
  ; GFX90A-NEXT:   [[PHI:%[0-9]+]]:agpr_32 = PHI [[COPY4]], %bb.0, %12.sub0, %bb.1
  ; GFX90A-NEXT:   [[PHI1:%[0-9]+]]:agpr_32 = PHI [[COPY3]], %bb.0, %12.sub1, %bb.1
  ; GFX90A-NEXT:   [[PHI2:%[0-9]+]]:agpr_32 = PHI [[COPY2]], %bb.0, %12.sub2, %bb.1
  ; GFX90A-NEXT:   [[PHI3:%[0-9]+]]:agpr_32 = PHI [[COPY1]], %bb.0, %12.sub3, %bb.1
  ; GFX90A-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[PHI3]]
  ; GFX90A-NEXT:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[PHI2]]
  ; GFX90A-NEXT:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[PHI1]]
  ; GFX90A-NEXT:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[PHI]]
  ; GFX90A-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:areg_128_align2 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY7]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY5]], %subreg.sub3
  ; GFX90A-NEXT:   [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1073741824, implicit $exec
  ; GFX90A-NEXT:   [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
  ; GFX90A-NEXT:   [[V_MFMA_F32_4X4X1F32_e64_:%[0-9]+]]:areg_128_align2 = V_MFMA_F32_4X4X1F32_e64 [[V_MOV_B32_e32_1]], [[V_MOV_B32_e32_]], [[REG_SEQUENCE]], 0, 0, 0, implicit $mode, implicit $exec
  ; GFX90A-NEXT:   S_CBRANCH_SCC1 %bb.1, implicit $scc
  ; GFX90A-NEXT: {{  $}}
  ; GFX90A-NEXT: bb.2:
  ; GFX90A-NEXT:   S_ENDPGM 0
  bb.0:
    liveins: $vgpr0, $scc
    successors: %bb.1

    %0:vgpr_32 = COPY $vgpr0

  bb.1:
    liveins: $scc
    successors: %bb.1, %bb.2

    %8:vgpr_32 = PHI %0, %bb.0, %16, %bb.1
    %9:vgpr_32 = PHI %0, %bb.0, %17, %bb.1
    %10:vgpr_32 = PHI %0, %bb.0, %18, %bb.1
    %11:vgpr_32 = PHI %0, %bb.0, %19, %bb.1
    %12:areg_128_align2 = REG_SEQUENCE %8, %subreg.sub0, %9, %subreg.sub1, %10, %subreg.sub2, %11, %subreg.sub3
    %13:vgpr_32 = V_MOV_B32_e32 1073741824, implicit $exec
    %14:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
    %15:areg_128_align2 = V_MFMA_F32_4X4X1F32_e64 %14:vgpr_32, %13:vgpr_32, %12:areg_128_align2, 0, 0, 0, implicit $mode, implicit $exec
    %16:vgpr_32 = COPY %15.sub0
    %17:vgpr_32 = COPY %15.sub1
    %18:vgpr_32 = COPY %15.sub2
    %19:vgpr_32 = COPY %15.sub3
    S_CBRANCH_SCC1 %bb.1, implicit $scc

  bb.2:
    S_ENDPGM 0
...

---
name: test_use_vgpr_temp
tracksRegLiveness: true

body: |
  ; GFX908-LABEL: name: test_use_vgpr_temp
  ; GFX908: bb.0:
  ; GFX908-NEXT:   successors: %bb.1(0x80000000)
  ; GFX908-NEXT:   liveins: $sgpr0, $scc
  ; GFX908-NEXT: {{  $}}
  ; GFX908-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $sgpr0
  ; GFX908-NEXT:   [[V_ACCVGPR_WRITE_B32_e64_:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 [[COPY]], implicit $exec
  ; GFX908-NEXT:   [[V_ACCVGPR_WRITE_B32_e64_1:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 [[COPY]], implicit $exec
  ; GFX908-NEXT:   [[V_ACCVGPR_WRITE_B32_e64_2:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 [[COPY]], implicit $exec
  ; GFX908-NEXT:   [[V_ACCVGPR_WRITE_B32_e64_3:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 [[COPY]], implicit $exec
  ; GFX908-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:areg_128_align2 = REG_SEQUENCE [[V_ACCVGPR_WRITE_B32_e64_]], %subreg.sub0, [[V_ACCVGPR_WRITE_B32_e64_1]], %subreg.sub1, [[V_ACCVGPR_WRITE_B32_e64_2]], %subreg.sub2, [[V_ACCVGPR_WRITE_B32_e64_3]], %subreg.sub3
  ; GFX908-NEXT:   [[V_ACCVGPR_READ_B32_e64_:%[0-9]+]]:vgpr_32 = V_ACCVGPR_READ_B32_e64 [[REG_SEQUENCE]].sub0, implicit $exec
  ; GFX908-NEXT:   [[COPY1:%[0-9]+]]:agpr_32 = COPY [[V_ACCVGPR_READ_B32_e64_]]
  ; GFX908-NEXT:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0
  ; GFX908-NEXT: {{  $}}
  ; GFX908-NEXT: bb.1:
  ; GFX908-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
  ; GFX908-NEXT:   liveins: $scc
  ; GFX908-NEXT: {{  $}}
  ; GFX908-NEXT:   [[PHI:%[0-9]+]]:agpr_32 = PHI [[COPY1]], %bb.0, %18.sub0, %bb.1
  ; GFX908-NEXT:   [[PHI1:%[0-9]+]]:agpr_32 = PHI [[COPY1]], %bb.0, %18.sub1, %bb.1
  ; GFX908-NEXT:   [[PHI2:%[0-9]+]]:agpr_32 = PHI [[COPY1]], %bb.0, %18.sub2, %bb.1
  ; GFX908-NEXT:   [[PHI3:%[0-9]+]]:agpr_32 = PHI [[COPY1]], %bb.0, %18.sub3, %bb.1
  ; GFX908-NEXT:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[PHI3]]
  ; GFX908-NEXT:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[PHI2]]
  ; GFX908-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[PHI1]]
  ; GFX908-NEXT:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[PHI]]
  ; GFX908-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:areg_128_align2 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX908-NEXT:   [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1073741824, implicit $exec
  ; GFX908-NEXT:   [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
  ; GFX908-NEXT:   [[V_MFMA_F32_4X4X1F32_e64_:%[0-9]+]]:areg_128_align2 = V_MFMA_F32_4X4X1F32_e64 [[V_MOV_B32_e32_1]], [[V_MOV_B32_e32_]], [[REG_SEQUENCE1]], 0, 0, 0, implicit $mode, implicit $exec
  ; GFX908-NEXT:   S_CBRANCH_SCC1 %bb.1, implicit $scc
  ; GFX908-NEXT: {{  $}}
  ; GFX908-NEXT: bb.2:
  ; GFX908-NEXT:   S_ENDPGM 0
  ; GFX90A-LABEL: name: test_use_vgpr_temp
  ; GFX90A: bb.0:
  ; GFX90A-NEXT:   successors: %bb.1(0x80000000)
  ; GFX90A-NEXT:   liveins: $sgpr0, $scc
  ; GFX90A-NEXT: {{  $}}
  ; GFX90A-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $sgpr0
  ; GFX90A-NEXT:   [[V_ACCVGPR_WRITE_B32_e64_:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 [[COPY]], implicit $exec
  ; GFX90A-NEXT:   [[V_ACCVGPR_WRITE_B32_e64_1:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 [[COPY]], implicit $exec
  ; GFX90A-NEXT:   [[V_ACCVGPR_WRITE_B32_e64_2:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 [[COPY]], implicit $exec
  ; GFX90A-NEXT:   [[V_ACCVGPR_WRITE_B32_e64_3:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 [[COPY]], implicit $exec
  ; GFX90A-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:areg_128_align2 = REG_SEQUENCE [[V_ACCVGPR_WRITE_B32_e64_]], %subreg.sub0, [[V_ACCVGPR_WRITE_B32_e64_1]], %subreg.sub1, [[V_ACCVGPR_WRITE_B32_e64_2]], %subreg.sub2, [[V_ACCVGPR_WRITE_B32_e64_3]], %subreg.sub3
  ; GFX90A-NEXT:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0
  ; GFX90A-NEXT: {{  $}}
  ; GFX90A-NEXT: bb.1:
  ; GFX90A-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
  ; GFX90A-NEXT:   liveins: $scc
  ; GFX90A-NEXT: {{  $}}
  ; GFX90A-NEXT:   [[PHI:%[0-9]+]]:agpr_32 = PHI [[REG_SEQUENCE]].sub0, %bb.0, %18.sub0, %bb.1
  ; GFX90A-NEXT:   [[PHI1:%[0-9]+]]:agpr_32 = PHI [[REG_SEQUENCE]].sub0, %bb.0, %18.sub1, %bb.1
  ; GFX90A-NEXT:   [[PHI2:%[0-9]+]]:agpr_32 = PHI [[REG_SEQUENCE]].sub0, %bb.0, %18.sub2, %bb.1
  ; GFX90A-NEXT:   [[PHI3:%[0-9]+]]:agpr_32 = PHI [[REG_SEQUENCE]].sub0, %bb.0, %18.sub3, %bb.1
  ; GFX90A-NEXT:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[PHI3]]
  ; GFX90A-NEXT:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[PHI2]]
  ; GFX90A-NEXT:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[PHI1]]
  ; GFX90A-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[PHI]]
  ; GFX90A-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:areg_128_align2 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY4]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY2]], %subreg.sub3
  ; GFX90A-NEXT:   [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1073741824, implicit $exec
  ; GFX90A-NEXT:   [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
  ; GFX90A-NEXT:   [[V_MFMA_F32_4X4X1F32_e64_:%[0-9]+]]:areg_128_align2 = V_MFMA_F32_4X4X1F32_e64 [[V_MOV_B32_e32_1]], [[V_MOV_B32_e32_]], [[REG_SEQUENCE1]], 0, 0, 0, implicit $mode, implicit $exec
  ; GFX90A-NEXT:   S_CBRANCH_SCC1 %bb.1, implicit $scc
  ; GFX90A-NEXT: {{  $}}
  ; GFX90A-NEXT: bb.2:
  ; GFX90A-NEXT:   S_ENDPGM 0
  bb.0:
    ; Tests that tryOptimizeAGPRPhis kicks in for GFX908.
    liveins: $sgpr0, $scc
    successors: %bb.1

    %1:vgpr_32 = COPY $sgpr0
    %2:agpr_32 = V_ACCVGPR_WRITE_B32_e64 %1, implicit $exec
    %3:agpr_32 = V_ACCVGPR_WRITE_B32_e64 %1, implicit $exec
    %4:agpr_32 = V_ACCVGPR_WRITE_B32_e64 %1, implicit $exec
    %5:agpr_32 = V_ACCVGPR_WRITE_B32_e64 %1, implicit $exec
    %6:areg_128_align2 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1, %4, %subreg.sub2, %5, %subreg.sub3
    %7:vgpr_32 = COPY %6.sub0
  bb.1:
    liveins: $scc
    successors: %bb.1, %bb.2

    %8:vgpr_32 = PHI %7, %bb.0, %16, %bb.1
    %9:vgpr_32 = PHI %7, %bb.0, %17, %bb.1
    %10:vgpr_32 = PHI %7, %bb.0, %18, %bb.1
    %11:vgpr_32 = PHI %7, %bb.0, %19, %bb.1
    %12:areg_128_align2 = REG_SEQUENCE %8, %subreg.sub0, %9, %subreg.sub1, %10, %subreg.sub2, %11, %subreg.sub3
    %13:vgpr_32 = V_MOV_B32_e32 1073741824, implicit $exec
    %14:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
    %15:areg_128_align2 = V_MFMA_F32_4X4X1F32_e64 %14:vgpr_32, %13:vgpr_32, %12:areg_128_align2, 0, 0, 0, implicit $mode, implicit $exec
    %16:vgpr_32 = COPY %15.sub0
    %17:vgpr_32 = COPY %15.sub1
    %18:vgpr_32 = COPY %15.sub2
    %19:vgpr_32 = COPY %15.sub3
    S_CBRANCH_SCC1 %bb.1, implicit $scc
  bb.2:
    S_ENDPGM 0
...
